FIG. 1 is a structural schematic diagram of a display panel in the prior art. As shown in FIG. 1, each pixel in the display panel is controlled by a gate line and a data line. A display panel of which the resolution is M*N should have M scan lines Gn (n=1, 2, . . . , M) and 3N data lines Dn (n=1, 2, . . . , 3N).
As the resolution of the display panel getting higher, the amount of the gate line and the amount of the fan-out line corresponding to the gate lines increase as well. The amount of the gate IC corresponding to the fan-out lines is increased when the scan lines are driven by single gate driving method, such that the area occupied by the fan-out block of the display panel is increased and therefore the design of narrow bezel cannot be realized. Besides, the width of the fan-out line corresponding to each scan line would be reduced as the resolution of the display panel getting higher if the area of the fan-out block remains the same, such that the line width of the fan-out lines is so small that the problem of line broken or signal delay would be occurred.